XCZU25DR
AMDZynq UltraScale+ RFSoCSoCThe XCZU25DR is a Zynq UltraScale+ RFSoC FPGA from AMD, built on a 16 nm process. It provides 310,000 LUT6 look-up tables (678,000 system logic cells), 620,000 flip-flops, 27.8 Mb of block RAM plus 13.5 Mb of UltraRAM and 3,145 DSP slices. Its processing system includes four Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 347 user I/O pins and 8 GTY transceivers at up to 28.21 Gb/s, with hard PCI Express Gen3 x16 blocks. It is available in 2 packages, from the E1156 (35 × 35 mm) to the G1517 (40 × 40 mm). Temperature grades: industrial, extended. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Zynq UltraScale+ RFSoC |
| Series | UltraScale+ |
| Process | 16 nm |
| Configuration memory | SRAM |
| Look-up tables (LUT6) | 310,000 |
| Logic block | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈496,000 |
| System logic cells | 678,000 |
| Flip-flops | 620,000 |
| Distributed RAM | 9,830 Kb |
| Block RAM | 27.8 Mb |
| UltraRAM | 13.5 Mb |
| DSP (DSP slice) | 3,145 |
| Max. user I/O | 347 |
|---|---|
| GTY transceivers | 8 × 28.21 Gb/s |
| PCI Express (PL) | Gen3 x16 |
| 100G Ethernet MAC | 1 |
| Analog / monitor | 8× 12-bit RF-ADC (4.096 GSPS), 8× 14-bit RF-DAC (6.554 GSPS) |
| Hard processor | 4× Arm Cortex-A53 @ 1.3 GHz |
| Real-time processor | Dual Arm Cortex-R5F |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | PS I/O | Transceivers |
|---|---|---|---|---|---|
| E1156 | 35 × 35 | 1.0 | 152 | 214 | 8 |
| G1517 | 40 × 40 | 1.0 | 347 | 214 | 8 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Industrial (I) | −40 to 100 °C | -1, -1L, -2, -2L |
| Extended (E) | 0 to 100 °C | -1, -2, -2L |
Alternatives to the XCZU25DR
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCZU9CGAMD Zynq UltraScale+ MPSoC | 274,000 LUT6 | 600K SLC | 2,520 | 32.1 Mb | 328 | 24 GTH 16.3 Gb/s | — | — |
| XCZU9EGAMD Zynq UltraScale+ MPSoC | 274,000 LUT6 | 600K SLC | 2,520 | 32.1 Mb | 328 | 24 GTH 16.3 Gb/s | — | — |
| XCZU15EGAMD Zynq UltraScale+ MPSoC | 341,000 LUT6 | 747K SLC | 3,528 | 26.2 Mb | 328 | 24 GTH 16.3 Gb/s | — | — |
| XC7Z100AMD Zynq 7000 | 277,400 LUT6 | 444K LC | 2,020 | 26.5 Mb | 400 | 16 GTX 12.5 Gb/s | Gen2 | — |
| XCZU7CGAMD Zynq UltraScale+ MPSoC | 230,000 LUT6 | 504K SLC | 1,728 | 11 Mb | 464 | 24 GTH 16.3 Gb/s | Gen3 | — |
| XCZU7EGAMD Zynq UltraScale+ MPSoC | 230,000 LUT6 | 504K SLC | 1,728 | 11 Mb | 464 | 24 GTH 16.3 Gb/s | Gen3 | — |
Compare side by side: XCZU25DR vs XCZU9CG, XCZU25DR vs XCZU9EG, XCZU25DR vs XCZU15EG.
Compare the XCZU25DR with up to three other FPGAs.
XCZU25DR quick facts
How many LUTs does the XCZU25DR have?
The XCZU25DR has 310,000 LUT6 look-up tables (678,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.
How many DSP blocks does the XCZU25DR have?
The XCZU25DR has 3,145 DSP slices and 27.8 Mb of block RAM plus 13.5 Mb of UltraRAM.
Does the XCZU25DR have transceivers?
Yes, 8 GTY transceivers at up to 28.21 Gb/s.
Does the XCZU25DR have a processor?
Yes. It includes a hard 4× Arm Cortex-A53 processor.
What are the alternatives to the XCZU25DR?
Devices of similar size in other families include XCZU9CG (AMD Zynq UltraScale+ MPSoC), XCZU9EG (AMD Zynq UltraScale+ MPSoC), XCZU15EG (AMD Zynq UltraScale+ MPSoC).
Which software is used to design with the XCZU25DR?
Designs for the XCZU25DR are built with AMD Vivado.
Other Zynq UltraScale+ RFSoC devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCZU64DR | 150,000 LUT6 | 328K SLC | 1,872 | 15.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU63DR | 180,000 LUT6 | 393K SLC | 1,200 | 17.6 Mb | 154 | 4 GTY 28.21 Gb/s | — | — |
| XCZU42DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 152 | 8 GTY 28.21 Gb/s | — | — |
| XCZU65DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU67DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU25DR | 310,000 LUT6 | 678K SLC | 3,145 | 27.8 Mb | 347 | 8 GTY 28.21 Gb/s | Gen3 | — |
| XCZU21DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 280 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU27DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU28DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU29DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU39DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU43DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU46DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 360 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU47DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU48DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU49DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen4 | — |
Source: AMD Zynq UltraScale+ RFSoC Product Selection Guide, XMP105 (v1.12.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.