XCZU63DR

AMDZynq UltraScale+ RFSoCSoC

The XCZU63DR is a Zynq UltraScale+ RFSoC FPGA from AMD, built on a 16 nm process. It provides 180,000 LUT6 look-up tables (393,000 system logic cells), 360,000 flip-flops, 17.6 Mb of block RAM plus 36.6 Mb of UltraRAM and 1,200 DSP slices. Its processing system includes four Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 154 user I/O pins and 4 GTY transceivers at up to 28.21 Gb/s. It comes in a single package, the E1156 (35 × 35 mm). Temperature grades: industrial. Designs are built with AMD Vivado.

180,000LUTs (LUT6)

1,200DSP slices

17.6 MbBlock RAM

36.6 MbUltraRAM

154Max. user I/O

4Transceivers (28.21 Gb/s)

4× A53Hard processor

Specifications

Vendor	AMD
Family	Zynq UltraScale+ RFSoC
Series	UltraScale+
Process	16 nm
Configuration memory	SRAM
Look-up tables (LUT6)	180,000
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈288,000
System logic cells	393,000
Flip-flops	360,000
Distributed RAM	5,601 Kb
Block RAM	17.6 Mb
UltraRAM	36.6 Mb
DSP (DSP slice)	1,200

Max. user I/O	154
GTY transceivers	4 × 28.21 Gb/s
PCI Express (PL)	None
100G Ethernet MAC	1
Analog / monitor	4× 14-bit RF-ADC (2.95 GSPS), 2× 14-bit RF-ADC (5.9 GSPS), 4× 14-bit RF-DAC (10 GSPS)
Hard processor	4× Arm Cortex-A53 @ 1.3 GHz
Real-time processor	Dual Arm Cortex-R5F
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
E1156	35 × 35	1.0	154	214	4

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Industrial (I)	−40 to 100 °C	-1, -1L, -2, -2L

Alternatives to the XCZU63DR

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCVE2302AMD Versal AI Edge	150,272 LUT6	329K SLC	464	5.4 Mb	238	8 GTYP 32.75 Gb/s	Gen4	—
XCVM1102AMD Versal Prime	150,272 LUT6	329K SLC	464	5 Mb	238	8 GTYP 32.75 Gb/s	Gen4	—
Ti375Efinix Titanium	362,880 LUT4	370K LE	1,344	27.5 Mb	337	16 SERDES 16 Gb/s	Gen4	—
SX 650Altera Stratix 10 GX/SX	207,360 ALMs	612K LE	1,152	49 Mb	392	24 XCVR/XCVR 28.3 Gb/s	Gen3	—
A5D 051Altera Agilex 5 D-Series	174,600 ALMs	515K LE	1,472	50.1 Mb	444	24 XCVR 28 Gb/s	Gen4	—
XC2VM3654AMD Versal Prime Gen 2	318,080 LUT6	696K SLC	1,428	22.2 Mb	310	24 GTYP 32.75 Gb/s	Gen5	—

Compare side by side: XCZU63DR vs XCVE2302, XCZU63DR vs XCVM1102, XCZU63DR vs Ti375.

Compare the XCZU63DR with up to three other FPGAs.

XCZU63DR quick facts

How many LUTs does the XCZU63DR have?

The XCZU63DR has 180,000 LUT6 look-up tables (393,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XCZU63DR have?

The XCZU63DR has 1,200 DSP slices and 17.6 Mb of block RAM plus 36.6 Mb of UltraRAM.

Does the XCZU63DR have transceivers?

Yes, 4 GTY transceivers at up to 28.21 Gb/s.

Does the XCZU63DR have a processor?

Yes. It includes a hard 4× Arm Cortex-A53 processor.

What are the alternatives to the XCZU63DR?

Devices of similar size in other families include XCVE2302 (AMD Versal AI Edge), XCVM1102 (AMD Versal Prime), Ti375 (Efinix Titanium).

Which software is used to design with the XCZU63DR?

Designs for the XCZU63DR are built with AMD Vivado.

Other Zynq UltraScale+ RFSoC devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCZU64DR	150,000 LUT6	328K SLC	1,872	15.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU63DR	180,000 LUT6	393K SLC	1,200	17.6 Mb	154	4 GTY 28.21 Gb/s	—	—
XCZU42DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	152	8 GTY 28.21 Gb/s	—	—
XCZU65DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU67DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU25DR	310,000 LUT6	678K SLC	3,145	27.8 Mb	347	8 GTY 28.21 Gb/s	Gen3	—
XCZU21DR	425,000 LUT6	930K SLC	4,272	38 Mb	280	16 GTY 28.21 Gb/s	Gen3	—
XCZU27DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen3	—
XCZU28DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen3	—
XCZU29DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen3	—
XCZU39DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen3	—
XCZU43DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU46DR	425,000 LUT6	930K SLC	4,272	38 Mb	360	16 GTY 28.21 Gb/s	Gen4	—
XCZU47DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU48DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU49DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen4	—

Source: AMD Zynq UltraScale+ RFSoC Product Selection Guide, XMP105 (v1.12.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.