XCZU64DR

AMDZynq UltraScale+ RFSoCSoC

The XCZU64DR is a Zynq UltraScale+ RFSoC FPGA from AMD, built on a 16 nm process. It provides 150,000 LUT6 look-up tables (328,000 system logic cells), 300,000 flip-flops, 15.8 Mb of block RAM plus 22.5 Mb of UltraRAM and 1,872 DSP slices. Its processing system includes four Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 154 user I/O pins and 8 GTY transceivers at up to 28.21 Gb/s. It comes in a single package, the E1156 (35 × 35 mm). Temperature grades: industrial. Designs are built with AMD Vivado.

150,000LUTs (LUT6)

1,872DSP slices

15.8 MbBlock RAM

22.5 MbUltraRAM

154Max. user I/O

8Transceivers (28.21 Gb/s)

4× A53Hard processor

Specifications

Vendor	AMD
Family	Zynq UltraScale+ RFSoC
Series	UltraScale+
Process	16 nm
Configuration memory	SRAM
Look-up tables (LUT6)	150,000
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈240,000
System logic cells	328,000
Flip-flops	300,000
Distributed RAM	4,669 Kb
Block RAM	15.8 Mb
UltraRAM	22.5 Mb
DSP (DSP slice)	1,872

Max. user I/O	154
GTY transceivers	8 × 28.21 Gb/s
PCI Express (PL)	None
100G Ethernet MAC	1
Analog / monitor	8× 14-bit RF-ADC (2.95 GSPS), 2× 14-bit RF-ADC (5.9 GSPS), 8× 14-bit RF-DAC (10 GSPS)
Hard processor	4× Arm Cortex-A53 @ 1.3 GHz
Real-time processor	Dual Arm Cortex-R5F
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
E1156	35 × 35	1.0	154	214	8

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Industrial (I)	−40 to 100 °C	-1, -1L, -2, -2L

Alternatives to the XCZU64DR

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCZU5CGAMD Zynq UltraScale+ MPSoC	117,000 LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3	—
XCZU5EGAMD Zynq UltraScale+ MPSoC	117,000 LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3	—
XCZU5EVAMD Zynq UltraScale+ MPSoC	117,000 LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3	—
Ti375Efinix Titanium	362,880 LUT4	370K LE	1,344	27.5 Mb	337	16 SERDES 16 Gb/s	Gen4	—
XCZU6CGAMD Zynq UltraScale+ MPSoC	215,000 LUT6	469K SLC	1,973	25.1 Mb	328	24 GTH 16.3 Gb/s	—	—
XCZU6EGAMD Zynq UltraScale+ MPSoC	215,000 LUT6	469K SLC	1,973	25.1 Mb	328	24 GTH 16.3 Gb/s	—	—

Compare side by side: XCZU64DR vs XCZU5CG, XCZU64DR vs XCZU5EG, XCZU64DR vs XCZU5EV.

Compare the XCZU64DR with up to three other FPGAs.

XCZU64DR quick facts

How many LUTs does the XCZU64DR have?

The XCZU64DR has 150,000 LUT6 look-up tables (328,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XCZU64DR have?

The XCZU64DR has 1,872 DSP slices and 15.8 Mb of block RAM plus 22.5 Mb of UltraRAM.

Does the XCZU64DR have transceivers?

Yes, 8 GTY transceivers at up to 28.21 Gb/s.

Does the XCZU64DR have a processor?

Yes. It includes a hard 4× Arm Cortex-A53 processor.

What are the alternatives to the XCZU64DR?

Devices of similar size in other families include XCZU5CG (AMD Zynq UltraScale+ MPSoC), XCZU5EG (AMD Zynq UltraScale+ MPSoC), XCZU5EV (AMD Zynq UltraScale+ MPSoC).

Which software is used to design with the XCZU64DR?

Designs for the XCZU64DR are built with AMD Vivado.

Other Zynq UltraScale+ RFSoC devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCZU64DR	150,000 LUT6	328K SLC	1,872	15.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU63DR	180,000 LUT6	393K SLC	1,200	17.6 Mb	154	4 GTY 28.21 Gb/s	—	—
XCZU42DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	152	8 GTY 28.21 Gb/s	—	—
XCZU65DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU67DR	224,000 LUT6	489K SLC	1,872	22.8 Mb	154	8 GTY 28.21 Gb/s	—	—
XCZU25DR	310,000 LUT6	678K SLC	3,145	27.8 Mb	347	8 GTY 28.21 Gb/s	Gen3	—
XCZU21DR	425,000 LUT6	930K SLC	4,272	38 Mb	280	16 GTY 28.21 Gb/s	Gen3	—
XCZU27DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen3	—
XCZU28DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen3	—
XCZU29DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen3	—
XCZU39DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen3	—
XCZU43DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU46DR	425,000 LUT6	930K SLC	4,272	38 Mb	360	16 GTY 28.21 Gb/s	Gen4	—
XCZU47DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU48DR	425,000 LUT6	930K SLC	4,272	38 Mb	347	16 GTY 28.21 Gb/s	Gen4	—
XCZU49DR	425,000 LUT6	930K SLC	4,272	38 Mb	408	16 GTY 28.21 Gb/s	Gen4	—

Source: AMD Zynq UltraScale+ RFSoC Product Selection Guide, XMP105 (v1.12.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.