5AGXA5
AlteraArria VSoCThe 5AGXA5 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 71,698 adaptive logic modules (ALMs) (190,000 logic elements (LEs)), 286,792 flip-flops, 11.5 Mb of block RAM and 600 variable-precision DSP blocks. It offers up to 544 user I/O pins and 24 XCVR transceivers at up to 6.5536 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 3 packages, from the F672 (27 × 27 mm) to the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Arria V |
| Series | Arria |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 71,698 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| LUT4 equivalent (approx.) | ≈143,396 |
| Logic elements (LEs) | 190,000 |
| Flip-flops | 286,792 |
| Distributed RAM | 1,173 Kb |
| Block RAM | 11.5 Mb (1180 × 10 Kb) |
| DSP (variable-precision DSP block) | 600 |
| Max. user I/O | 544 |
|---|---|
| XCVR transceivers | 24 × 6.5536 Gb/s |
| PCI Express | 2× Gen2 x4 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F672 | 27 × 27 | 1.0 | 336 | 9 |
| F896 | 31 × 31 | 1.0 | 384 | 18 |
| F1152 | 35 × 35 | 1.0 | 544 | 24 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5AGXA5
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5SGSD3Altera Stratix V | 89,000 ALMs | 236K LE | 600 | 13.4 Mb | 432 | 24 GX 14.1 Gb/s | Gen3 | — |
| XC6VLX130TAMD Virtex-6 | 80,000 LUT6 | 128K LC | 480 | 9.3 Mb | 600 | 20 GTX 6.6 Gb/s | Gen2 | — |
| XC6VLX195TAMD Virtex-6 | 124,800 LUT6 | 200K LC | 640 | 12.1 Mb | 600 | 20 GTX 6.6 Gb/s | Gen2 | — |
| EP2AGZ225Altera Arria II | 89,600 ALMs | 224K LE | 800 | 10.8 Mb | 734 | 24 XCVR 6.375 Gb/s | Gen2 | — |
| MPF200TMicrochip PolarFire | 192,000 LUT4 | 192K LE | 588 | 12 Mb | 368 | 16 SERDES 12.7 Gb/s | Gen2 | — |
| EP2AGX190Altera Arria II | 76,120 ALMs | 181K LE | 656 | 7.4 Mb | 612 | 16 XCVR 6.375 Gb/s | Gen1 | — |
Compare side by side: 5AGXA5 vs 5SGSD3, 5AGXA5 vs XC6VLX130T, 5AGXA5 vs XC6VLX195T, 5AGXA5 vs EP2AGX190.
Compare the 5AGXA5 with up to three other FPGAs.
5AGXA5 quick facts
How many LUTs does the 5AGXA5 have?
The 5AGXA5 has 71,698 adaptive logic modules (ALMs) (190,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5AGXA5 have?
The 5AGXA5 has 600 variable-precision DSP blocks and 11.5 Mb of block RAM.
Does the 5AGXA5 have transceivers?
Yes, 24 XCVR transceivers at up to 6.5536 Gb/s.
What are the alternatives to the 5AGXA5?
Devices of similar size in other families include 5SGSD3 (Altera Stratix V), XC6VLX130T (AMD Virtex-6), XC6VLX195T (AMD Virtex-6).
Which software is used to design with the 5AGXA5?
Designs for the 5AGXA5 are built with Altera Quartus Prime.
Other Arria V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5AGXA1 | 28,302 ALMs | 75K LE | 240 | 7.8 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGXA3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 7 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXA5 | 71,698 ALMs | 190K LE | 600 | 11.5 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE1 | 83,020 ALMs | 220K LE | 800 | 11.4 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXA7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB1 | 113,208 ALMs | 300K LE | 920 | 14.8 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASXB3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE3 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE5 | 150,960 ALMs | 400K LE | 1,092 | 28.1 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB5 | 158,491 ALMs | 420K LE | 1,092 | 20.1 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE7 | 169,800 ALMs | 450K LE | 1,139 | 33.2 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5ASXB5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 26 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.