GX 400
AlteraStratix 10 GX/SXSoCThe GX 400 is a Stratix 10 GX/SX FPGA from Altera, built on a 14 nm process. It provides 128,160 adaptive logic modules (ALMs) (378,000 logic elements (LEs)), about 256,320 LUT4 equivalents, 30 Mb of block RAM and 648 variable-precision DSP blocks. It offers up to 374 user I/O pins and 24 XCVR/XCVR transceivers at up to 28.3 Gb/s, with hard PCI Express Gen3 x16 blocks. It comes in a single package, the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Stratix 10 GX/SX |
| Series | Stratix |
| Process | 14 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 256,320 |
| Adaptive logic modules (ALMs) | 128,160 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 378,000 |
| Distributed RAM | 2,048 Kb |
| Block RAM | 30 Mb (1537 × 20 Kb) |
| DSP (variable-precision DSP block) | 648 |
| Max. user I/O | 374 |
|---|---|
| XCVR transceivers | 16 × 28.3 Gb/s |
| XCVR transceivers | 8 × 17.4 Gb/s |
| PCI Express | Gen3 x16 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F1152 | 35 × 35 | 1.0 | 374 | 24 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the GX 400
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| LAV-AT-G50Lattice Avant-G | 255K 255K LUT4 | 409K LC | 1,120 | 22.7 Mb | 298 | 16 SERDES 12.5 Gb/s | — |
| LAV-AT-X50Lattice Avant-X | 255K 255K LUT4 | 409K LC | 1,120 | 22.7 Mb | 298 | 16 SERDES 25 Gb/s | — |
| MPF300TMicrochip PolarFire | 300K 300K LUT4 | 300K LE | 924 | 18.6 Mb | 512 | 16 SERDES 12.7 Gb/s | Gen2 |
| 10AX032Altera Arria 10 | 237K 119K ALMs | 419K LE | 985 | 17.4 Mb | 384 | 24 XCVR 17.4 Gb/s | Gen3 |
| XC2KU030PAMD Kintex UltraScale+ Gen 2 | 240K 150K LUT6 | 328K SLC | 1,248 | 11.8 Mb | 342 | 16 GTY 32.75 Gb/s | Gen4 |
| XC7VX330TAMD Virtex-7 | 326K 204K LUT6 | 326K LC | 1,120 | 26.4 Mb | 700 | 28 GTH 13.1 Gb/s | Gen3 |
Compare side by side: GX 400 vs LAV-AT-G50, GX 400 vs LAV-AT-X50, GX 400 vs MPF300T.
GX 400 quick facts
How many LUTs does the GX 400 have?
The GX 400 has 128,160 adaptive logic modules (ALMs), about 256,320 LUT4 equivalents (378,000 logic elements (les) as published by Altera).
How many DSP blocks does the GX 400 have?
The GX 400 has 648 variable-precision DSP blocks and 30 Mb of block RAM.
Does the GX 400 have transceivers?
Yes, 24 XCVR/XCVR transceivers at up to 28.3 Gb/s.
What are the alternatives to the GX 400?
Devices of similar size in other families include LAV-AT-G50 (Lattice Avant-G), LAV-AT-X50 (Lattice Avant-X), MPF300T (Microchip PolarFire).
Which software is used to design with the GX 400?
Designs for the GX 400 are built with Altera Quartus Prime.
Other Stratix 10 GX/SX devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| GX 400 | 256K 128K ALMs | 378K LE | 648 | 30 Mb | 374 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 400 | 256K 128K ALMs | 378K LE | 648 | 30 Mb | 374 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 650 | 415K 207K ALMs | 612K LE | 1,152 | 49 Mb | 392 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 650 | 415K 207K ALMs | 612K LE | 1,152 | 49 Mb | 392 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 850 | 570K 285K ALMs | 841K LE | 2,016 | 68 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 850 | 570K 285K ALMs | 841K LE | 2,016 | 68 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 1100 | 899K 449K ALMs | 1325K LE | 2,592 | 107 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 1100 | 899K 449K ALMs | 1325K LE | 2,592 | 107 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 1650 | 1101K 551K ALMs | 1624K LE | 3,145 | 114 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 1650 | 1101K 551K ALMs | 1624K LE | 3,145 | 114 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2100 | 1359K 680K ALMs | 2005K LE | 3,744 | 127 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2100 | 1359K 680K ALMs | 2005K LE | 3,744 | 127 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2500 | 1642K 821K ALMs | 2422K LE | 5,011 | 195 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2500 | 1642K 821K ALMs | 2422K LE | 5,011 | 195 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2800 | 1866K 933K ALMs | 2753K LE | 5,760 | 229 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2800 | 1866K 933K ALMs | 2753K LE | 5,760 | 229 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
Source: Altera Stratix 10 GX/SX FPGA Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.