GX 650
AlteraStratix 10 GX/SXSoCThe GX 650 is a Stratix 10 GX/SX FPGA from Altera, built on a 14 nm process. It provides 207,360 adaptive logic modules (ALMs) (612,000 logic elements (LEs)), about 414,720 LUT4 equivalents, 49 Mb of block RAM and 1,152 variable-precision DSP blocks. It offers up to 392 user I/O pins and 24 XCVR/XCVR transceivers at up to 28.3 Gb/s, with hard PCI Express Gen3 x16 blocks. It comes in a single package, the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Stratix 10 GX/SX |
| Series | Stratix |
| Process | 14 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 414,720 |
| Adaptive logic modules (ALMs) | 207,360 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 612,000 |
| Distributed RAM | 3,072 Kb |
| Block RAM | 49 Mb (2489 × 20 Kb) |
| DSP (variable-precision DSP block) | 1,152 |
| Max. user I/O | 392 |
|---|---|
| XCVR transceivers | 16 × 28.3 Gb/s |
| XCVR transceivers | 8 × 17.4 Gb/s |
| PCI Express | Gen3 x16 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F1152 | 35 × 35 | 1.0 | 392 | 24 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the GX 650
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| XC2KU050PAMD Kintex UltraScale+ Gen 2 | 360K 225K LUT6 | 491K SLC | 1,872 | 17.7 Mb | 516 | 24 GTY 32.75 Gb/s | Gen4 |
| XC2KU040PAMD Kintex UltraScale+ Gen 2 | 299K 187K LUT6 | 410K SLC | 1,560 | 14.8 Mb | 474 | 16 GTY 32.75 Gb/s | Gen4 |
| LAV-AT-G70Lattice Avant-G | 397K 397K LUT4 | 637K LC | 1,800 | 35.6 Mb | 554 | 28 SERDES 12.5 Gb/s | — |
| LAV-AT-X70Lattice Avant-X | 397K 397K LUT4 | 637K LC | 1,800 | 35.6 Mb | 554 | 28 SERDES 25 Gb/s | — |
| MPF500TMicrochip PolarFire | 481K 481K LUT4 | 481K LE | 1,480 | 29.7 Mb | 584 | 24 SERDES 12.7 Gb/s | Gen2 |
| 10AX048Altera Arria 10 | 364K 182K ALMs | 629K LE | 1,368 | 28.1 Mb | 492 | 36 XCVR 17.4 Gb/s | Gen3 |
Compare side by side: GX 650 vs XC2KU050P, GX 650 vs XC2KU040P, GX 650 vs LAV-AT-G70.
GX 650 quick facts
How many LUTs does the GX 650 have?
The GX 650 has 207,360 adaptive logic modules (ALMs), about 414,720 LUT4 equivalents (612,000 logic elements (les) as published by Altera).
How many DSP blocks does the GX 650 have?
The GX 650 has 1,152 variable-precision DSP blocks and 49 Mb of block RAM.
Does the GX 650 have transceivers?
Yes, 24 XCVR/XCVR transceivers at up to 28.3 Gb/s.
What are the alternatives to the GX 650?
Devices of similar size in other families include XC2KU050P (AMD Kintex UltraScale+ Gen 2), XC2KU040P (AMD Kintex UltraScale+ Gen 2), LAV-AT-G70 (Lattice Avant-G).
Which software is used to design with the GX 650?
Designs for the GX 650 are built with Altera Quartus Prime.
Other Stratix 10 GX/SX devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| GX 400 | 256K 128K ALMs | 378K LE | 648 | 30 Mb | 374 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 400 | 256K 128K ALMs | 378K LE | 648 | 30 Mb | 374 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 650 | 415K 207K ALMs | 612K LE | 1,152 | 49 Mb | 392 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 650 | 415K 207K ALMs | 612K LE | 1,152 | 49 Mb | 392 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 850 | 570K 285K ALMs | 841K LE | 2,016 | 68 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 850 | 570K 285K ALMs | 841K LE | 2,016 | 68 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 1100 | 899K 449K ALMs | 1325K LE | 2,592 | 107 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 1100 | 899K 449K ALMs | 1325K LE | 2,592 | 107 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 1650 | 1101K 551K ALMs | 1624K LE | 3,145 | 114 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 1650 | 1101K 551K ALMs | 1624K LE | 3,145 | 114 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2100 | 1359K 680K ALMs | 2005K LE | 3,744 | 127 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2100 | 1359K 680K ALMs | 2005K LE | 3,744 | 127 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2500 | 1642K 821K ALMs | 2422K LE | 5,011 | 195 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2500 | 1642K 821K ALMs | 2422K LE | 5,011 | 195 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| GX 2800 | 1866K 933K ALMs | 2753K LE | 5,760 | 229 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2800 | 1866K 933K ALMs | 2753K LE | 5,760 | 229 Mb | 1,160 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
Source: Altera Stratix 10 GX/SX FPGA Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.