5AGTD3
AlteraArria VSoCThe 5AGTD3 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 136,880 adaptive logic modules (ALMs) (362,000 logic elements (LEs)), 547,520 flip-flops, 16.9 Mb of block RAM and 1,045 variable-precision DSP blocks. It offers up to 704 user I/O pins and 18 XCVR/XCVR transceivers at up to 10.3125 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 3 packages, from the F896 (31 × 31 mm) to the F1517 (40 × 40 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Arria V |
| Series | Arria |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 136,880 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| LUT4 equivalent (approx.) | ≈273,760 |
| Logic elements (LEs) | 362,000 |
| Flip-flops | 547,520 |
| Distributed RAM | 2,098 Kb |
| Block RAM | 16.9 Mb (1726 × 10 Kb) |
| DSP (variable-precision DSP block) | 1,045 |
| Max. user I/O | 704 |
|---|---|
| XCVR transceivers | 6 × 6.5536 Gb/s |
| XCVR transceivers | 12 × 10.3125 Gb/s |
| PCI Express | 2× Gen2 x4 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F896 | 31 × 31 | 1.0 | 384 | 14 |
| F1152 | 35 × 35 | 1.0 | 544 | 18 |
| F1517 | 40 × 40 | 1.0 | 704 | 18 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5AGTD3
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| EP2AGZ350Altera Arria II | 139,400 ALMs | 349K LE | 1,040 | 16 Mb | 734 | 24 XCVR 6.375 Gb/s | Gen2 | — |
| MPF300TMicrochip PolarFire | 300,000 LUT4 | 300K LE | 924 | 18.6 Mb | 512 | 16 SERDES 12.7 Gb/s | Gen2 | 882 polarfireeval |
| EP2AGZ300Altera Arria II | 119,200 ALMs | 298K LE | 920 | 14.3 Mb | 734 | 24 XCVR 6.375 Gb/s | Gen2 | — |
| XC7K325TAMD Kintex-7 | 203,800 LUT6 | 326K LC | 840 | 15.6 Mb | 500 | 16 GTX 12.5 Gb/s | Gen2 | 967 genesys2 |
| XC6VLX240TAMD Virtex-6 | 150,720 LUT6 | 241K LC | 768 | 14.6 Mb | 720 | 24 GTX 6.6 Gb/s | Gen2 | — |
| 5SGSD4Altera Stratix V | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | — |
Compare side by side: 5AGTD3 vs EP2AGZ350, 5AGTD3 vs MPF300T, 5AGTD3 vs EP2AGZ300, 5AGTD3 vs XC7K325T.
Compare the 5AGTD3 with up to three other FPGAs.
5AGTD3 quick facts
How many LUTs does the 5AGTD3 have?
The 5AGTD3 has 136,880 adaptive logic modules (ALMs) (362,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5AGTD3 have?
The 5AGTD3 has 1,045 variable-precision DSP blocks and 16.9 Mb of block RAM.
Does the 5AGTD3 have transceivers?
Yes, 18 XCVR/XCVR transceivers at up to 10.3125 Gb/s.
What are the alternatives to the 5AGTD3?
Devices of similar size in other families include EP2AGZ350 (Altera Arria II), MPF300T (Microchip PolarFire), EP2AGZ300 (Altera Arria II).
Which software is used to design with the 5AGTD3?
Designs for the 5AGTD3 are built with Altera Quartus Prime.
Other Arria V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5AGXA1 | 28,302 ALMs | 75K LE | 240 | 7.8 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGXA3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 7 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXA5 | 71,698 ALMs | 190K LE | 600 | 11.5 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE1 | 83,020 ALMs | 220K LE | 800 | 11.4 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXA7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB1 | 113,208 ALMs | 300K LE | 920 | 14.8 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASXB3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE3 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE5 | 150,960 ALMs | 400K LE | 1,092 | 28.1 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB5 | 158,491 ALMs | 420K LE | 1,092 | 20.1 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE7 | 169,800 ALMs | 450K LE | 1,139 | 33.2 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5ASXB5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 26 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.