XC2VP3202

AMDVersal Premium Gen 2SoC

The XC2VP3202 is a Versal Premium Gen 2 SoC FPGA from AMD. It provides 797,056 LUT6 look-up tables (1,743,560 system logic cells), 1,594,112 flip-flops, 53 Mb of block RAM plus 101 Mb of UltraRAM and 4,004 DSP Engines. Its processing system includes two Arm Cortex-A72 cores, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 438 user I/O pins and 32 GTM2 transceivers at up to 112 Gb/s, with hard PCI Express Gen6 x8 blocks. It is available in 2 packages, from the NSVO1369 ( mm) to the VSVJ1760 ( mm). Designs are built with AMD Vivado.

797,056LUTs (LUT6)

4,004DSP Engines

53 MbBlock RAM

101 MbUltraRAM

438Max. user I/O

32Transceivers (112 Gb/s)

2× A72Hard processor

Specifications

Vendor	AMD
Family	Versal Premium Gen 2
Series	Versal
Configuration memory	SRAM
Look-up tables (LUT6)	797,056
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈1,275,290
System logic cells	1,743,560
Flip-flops	1,594,112
Distributed RAM	24,576 Kb
Block RAM	53 Mb
UltraRAM	101 Mb
DSP (DSP Engine)	4,004

Max. user I/O	438
GTM2 transceivers	32 × 112 Gb/s
PCI Express (PL)	2× Gen6 x8
Analog / monitor	System Monitor
Hard processor	2× Arm Cortex-A72
Real-time processor	Dual Arm Cortex-R5F
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
NSVO1369		0.92	328	52	32
VSVJ1760		0.92	438	78	32

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the XC2VP3202

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCVR1902AMD Versal RF	1,130,880 LUT6	2474K SLC	3,976	80 Mb	470	20 GTM2 112 Gb/s	Gen5	—
XCVR1952AMD Versal RF	1,130,880 LUT6	2474K SLC	3,976	80 Mb	470	20 GTM2 112 Gb/s	Gen5	—
AGF 014Altera Agilex 7 F-Series	487,200 ALMs	1437K LE	4,510	139 Mb	768	32 XCVR 58 Gb/s	—	2,970 intel_dk-dev-agf014ea
AGRW014Altera Agilex 9 Direct RF	487,200 ALMs	1437K LE	4,510	139 Mb	434	16 XCVR 58 Gb/s	Gen4	—
Ti2000Efinix Titanium	— 1974K LEs, LUTs not published	1974K LE	3,808	117 Mb	480	40 SERDES 25.8 Gb/s	Gen4	—
A5D 160Altera Agilex 5 D-Series	548,000 ALMs	1617K LE	4,968	156.4 Mb	888	48 XCVR 28 Gb/s	Gen4	—

Compare side by side: XC2VP3202 vs XCVR1902, XC2VP3202 vs XCVR1952, XC2VP3202 vs AGF 014, XC2VP3202 vs AGRW014, XC2VP3202 vs Ti2000.

Compare the XC2VP3202 with up to three other FPGAs.

XC2VP3202 quick facts

How many LUTs does the XC2VP3202 have?

The XC2VP3202 has 797,056 LUT6 look-up tables (1,743,560 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC2VP3202 have?

The XC2VP3202 has 4,004 DSP Engines and 53 Mb of block RAM plus 101 Mb of UltraRAM.

Does the XC2VP3202 have transceivers?

Yes, 32 GTM2 transceivers at up to 112 Gb/s.

Does the XC2VP3202 have a processor?

Yes. It includes a hard 2× Arm Cortex-A72 processor.

What are the alternatives to the XC2VP3202?

Devices of similar size in other families include XCVR1902 (AMD Versal RF), XCVR1952 (AMD Versal RF), AGF 014 (Altera Agilex 7 F-Series).

Which software is used to design with the XC2VP3202?

Designs for the XC2VP3202 are built with AMD Vivado.

Other Versal Premium Gen 2 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC2VP3102	643,456 LUT6	1408K SLC	3,332	44 Mb	438	32 GTM2 112 Gb/s	Gen6	—
XC2VP3202	797,056 LUT6	1744K SLC	4,004	53 Mb	438	32 GTM2 112 Gb/s	Gen6	—
XC2VP3402	1,170,816 LUT6	2561K SLC	6,080	78 Mb	736	56 GTM2 112 Gb/s	Gen6	—
XC2VP3502	1,496,448 LUT6	3273K SLC	2,856	99 Mb	736	72 GTM2 112 Gb/s	Gen6	—
XC2VP3602	1,496,448 LUT6	3273K SLC	7,616	99 Mb	736	72 GTM2 112 Gb/s	Gen6	—

Source: AMD Versal Premium Gen 2 Series Product Selection Guide, XMP510 (v1.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.