XC6SLX16

AMDSpartan-6

The XC6SLX16 is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 9,112 LUT6 look-up tables (14,579 logic cells), 18,224 flip-flops, 0.6 Mb of block RAM and 32 DSP48A1 slices. It offers up to 232 user I/O pins. It is available in 4 packages, from the CPG196 (8 × 8 mm) to the FTG256 (17 × 17 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.

9,112LUTs (LUT6)

32DSP48A1 slices

0.6 MbBlock RAM

232Max. user I/O

—Transceivers

Specifications

Vendor	AMD
Family	Spartan-6
Series	6 Series
Process	45 nm
Configuration memory	SRAM
Look-up tables (LUT6)	9,112
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈14,579
Logic cells	14,579
Flip-flops	18,224
Distributed RAM	136 Kb
Block RAM	0.6 Mb (32 × 18 Kb)
DSP (DSP48A1 slice)	32
Clock management tiles	2

Max. user I/O	232
Transceivers	None
PCI Express	None
Hard memory controller	2 × MCB (DDR/DDR2/DDR3/LPDDR)
Analog / monitor	None
Design tool	AMD ISE Design Suite

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
CPG196	8 × 8	0.5	106	—
CSG225	13 × 13	0.8	160	—
FTG256	17 × 17	1.0	186	—
CSG324	15 × 15	0.8	232	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-3, -3N, -2, -1L
Industrial (I)	−40 to 100 °C	-3, -3N, -2, -1L

Alternatives to the XC6SLX16

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
LFE5U-12Lattice ECP5	12,000 LUT4	—	28	0.6 Mb	197	—	—	—
T13Efinix Trion	— 12.8K LEs, LUTs not published	12.8K LE	24	0.7 Mb	195	—	—	—
10M16Altera MAX 10	16,000 LUT4	16K LE	45	0.5 Mb	320	—	—	—
T20Efinix Trion	— 19.7K LEs, LUTs not published	19.7K LE	36	1 Mb	230	—	—	—
EP4CE10Altera Cyclone IV	10,000 LUT4	10K LE	23	0.4 Mb	179	—	—	—
10CL010Altera Cyclone 10 LP	10,000 LUT4	10K LE	23	0.4 Mb	176	—	—	—

Compare side by side: XC6SLX16 vs LFE5U-12, XC6SLX16 vs T13, XC6SLX16 vs 10M16.

Compare the XC6SLX16 with up to three other FPGAs.

XC6SLX16 quick facts

How many LUTs does the XC6SLX16 have?

The XC6SLX16 has 9,112 LUT6 look-up tables (14,579 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC6SLX16 have?

The XC6SLX16 has 32 DSP48A1 slices and 0.6 Mb of block RAM.

Does the XC6SLX16 have transceivers?

No, the XC6SLX16 has no multi-gigabit transceivers. Its user I/O supports up to 232 pins.

What are the alternatives to the XC6SLX16?

Devices of similar size in other families include LFE5U-12 (Lattice ECP5), T13 (Efinix Trion), 10M16 (Altera MAX 10).

Which software is used to design with the XC6SLX16?

Designs for the XC6SLX16 are built with AMD ISE Design Suite.

Other Spartan-6 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC6SLX4	2,400 LUT6	3.8K LC	8	0.2 Mb	132	—	—	—
XC6SLX9	5,720 LUT6	9.2K LC	16	0.6 Mb	200	—	—	—
XC6SLX16	9,112 LUT6	14.6K LC	32	0.6 Mb	232	—	—	—
XC6SLX25	15,032 LUT6	24.1K LC	38	0.9 Mb	266	—	—	—
XC6SLX25T	15,032 LUT6	24.1K LC	38	0.9 Mb	250	2 GTP 3.2 Gb/s	Gen1	—
XC6SLX45	27,288 LUT6	43.7K LC	58	2 Mb	358	—	—	—
XC6SLX45T	27,288 LUT6	43.7K LC	58	2 Mb	296	4 GTP 3.2 Gb/s	Gen1	—
XC6SLX75	46,648 LUT6	74.6K LC	132	3 Mb	408	—	—	—
XC6SLX75T	46,648 LUT6	74.6K LC	132	3 Mb	348	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX100	63,288 LUT6	101K LC	180	4.7 Mb	480	—	—	—
XC6SLX100T	63,288 LUT6	101K LC	180	4.7 Mb	498	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX150	92,152 LUT6	147K LC	180	4.7 Mb	576	—	—	—
XC6SLX150T	92,152 LUT6	147K LC	180	4.7 Mb	540	8 GTP 3.2 Gb/s	Gen1	—

Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.