XC6SLX9

AMDSpartan-6

The XC6SLX9 is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 5,720 LUT6 look-up tables (9,152 logic cells), 11,440 flip-flops, 0.6 Mb of block RAM and 16 DSP48A1 slices. It offers up to 200 user I/O pins. It is available in 5 packages, from the CPG196 (8 × 8 mm) to the TQG144 (20 × 20 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.

5,720LUTs (LUT6)

16DSP48A1 slices

0.6 MbBlock RAM

200Max. user I/O

—Transceivers

Specifications

Vendor	AMD
Family	Spartan-6
Series	6 Series
Process	45 nm
Configuration memory	SRAM
Look-up tables (LUT6)	5,720
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈9,152
Logic cells	9,152
Flip-flops	11,440
Distributed RAM	90 Kb
Block RAM	0.6 Mb (32 × 18 Kb)
DSP (DSP48A1 slice)	16
Clock management tiles	2

Max. user I/O	200
Transceivers	None
PCI Express	None
Hard memory controller	2 × MCB (DDR/DDR2/DDR3/LPDDR)
Analog / monitor	None
Design tool	AMD ISE Design Suite

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
CPG196	8 × 8	0.5	106	—
TQG144	20 × 20	0.5	102	—
CSG225	13 × 13	0.8	160	—
FTG256	17 × 17	1.0	186	—
CSG324	15 × 15	0.8	200	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-3, -3N, -2, -1L
Industrial (I)	−40 to 100 °C	-3, -3N, -2, -1L

Alternatives to the XC6SLX9

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
LFXP2-8ELattice LatticeXP2	8,000 LUT4	—	16	0.2 Mb	201	—	—	—
GW1N-9Gowin LittleBee	8,640 LUT4	—	20	0.5 Mb	276	—	—	—
GW1NR-9Gowin LittleBee	8,640 LUT4	—	20	0.5 Mb	276	—	—	—
EP4CE10Altera Cyclone IV	10,000 LUT4	10K LE	23	0.4 Mb	179	—	—	—
10CL010Altera Cyclone 10 LP	10,000 LUT4	10K LE	23	0.4 Mb	176	—	—	—
LFMXO5-15DLattice MachXO5-NX	11,667 LUT4	14K LC	16	0.3 Mb	305	—	—	—

Compare side by side: XC6SLX9 vs LFXP2-8E, XC6SLX9 vs GW1N-9, XC6SLX9 vs GW1NR-9, XC6SLX9 vs LFMXO5-15D.

Compare the XC6SLX9 with up to three other FPGAs.

XC6SLX9 quick facts

How many LUTs does the XC6SLX9 have?

The XC6SLX9 has 5,720 LUT6 look-up tables (9,152 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC6SLX9 have?

The XC6SLX9 has 16 DSP48A1 slices and 0.6 Mb of block RAM.

Does the XC6SLX9 have transceivers?

No, the XC6SLX9 has no multi-gigabit transceivers. Its user I/O supports up to 200 pins.

What are the alternatives to the XC6SLX9?

Devices of similar size in other families include LFXP2-8E (Lattice LatticeXP2), GW1N-9 (Gowin LittleBee), GW1NR-9 (Gowin LittleBee).

Which software is used to design with the XC6SLX9?

Designs for the XC6SLX9 are built with AMD ISE Design Suite.

Other Spartan-6 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC6SLX4	2,400 LUT6	3.8K LC	8	0.2 Mb	132	—	—	—
XC6SLX9	5,720 LUT6	9.2K LC	16	0.6 Mb	200	—	—	—
XC6SLX16	9,112 LUT6	14.6K LC	32	0.6 Mb	232	—	—	—
XC6SLX25	15,032 LUT6	24.1K LC	38	0.9 Mb	266	—	—	—
XC6SLX25T	15,032 LUT6	24.1K LC	38	0.9 Mb	250	2 GTP 3.2 Gb/s	Gen1	—
XC6SLX45	27,288 LUT6	43.7K LC	58	2 Mb	358	—	—	—
XC6SLX45T	27,288 LUT6	43.7K LC	58	2 Mb	296	4 GTP 3.2 Gb/s	Gen1	—
XC6SLX75	46,648 LUT6	74.6K LC	132	3 Mb	408	—	—	—
XC6SLX75T	46,648 LUT6	74.6K LC	132	3 Mb	348	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX100	63,288 LUT6	101K LC	180	4.7 Mb	480	—	—	—
XC6SLX100T	63,288 LUT6	101K LC	180	4.7 Mb	498	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX150	92,152 LUT6	147K LC	180	4.7 Mb	576	—	—	—
XC6SLX150T	92,152 LUT6	147K LC	180	4.7 Mb	540	8 GTP 3.2 Gb/s	Gen1	—

Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.