XC6SLX25T
AMDSpartan-6The XC6SLX25T is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 15,032 LUT6 look-up tables (24,051 logic cells), 30,064 flip-flops, 0.9 Mb of block RAM and 38 DSP48A1 slices. It offers up to 250 user I/O pins and 2 GTP transceivers at up to 3.2 Gb/s, with hard PCI Express Gen1 x1 blocks. It is available in 2 packages, from the CSG324 (15 × 15 mm) to the FGG484 (23 × 23 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.
Specifications
| Vendor | AMD |
|---|---|
| Family | Spartan-6 |
| Series | 6 Series |
| Process | 45 nm |
| Configuration memory | SRAM |
| Look-up tables (LUT6) | 15,032 |
| Logic block | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈24,051 |
| Logic cells | 24,051 |
| Flip-flops | 30,064 |
| Distributed RAM | 229 Kb |
| Block RAM | 0.9 Mb (52 × 18 Kb) |
| DSP (DSP48A1 slice) | 38 |
| Clock management tiles | 2 |
| Max. user I/O | 250 |
|---|---|
| GTP transceivers | 2 × 3.2 Gb/s |
| PCI Express | Gen1 x1 |
| Hard memory controller | 2 × MCB (DDR/DDR2/DDR3/LPDDR) |
| Analog / monitor | None |
| Design tool | AMD ISE Design Suite |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| CSG324 | 15 × 15 | 0.8 | 190 | 2 |
| FGG484 | 23 × 23 | 1.0 | 250 | 2 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Commercial (C) | 0 to 85 °C | -3, -3N, -2 |
| Industrial (I) | −40 to 100 °C | -3, -3N, -2 |
Alternatives to the XC6SLX25T
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| LFE5UM-25Lattice ECP5 | 24,000 LUT4 | — | 28 | 1 Mb | 197 | 2 SERDES 3.2 Gb/s | — | — |
| LFE5UM5G-25Lattice ECP5 | 24,000 LUT4 | — | 28 | 1 Mb | 197 | 2 SERDES 5 Gb/s | — | — |
| M2GL025Microchip IGLOO2 | 27,696 LUT4 | 27.7K LE | 34 | 0.5 Mb | 267 | 4 SERDES 5 Gb/s | Gen2 | — |
| LFMXO5-30TDLattice MachXO5-NX | 25,000 LUT4 | 30K LC | 48 | 0.8 Mb | 368 | 1 SERDES | Gen2 | — |
| EP4CGX22Altera Cyclone IV | 21,000 LUT4 | 21K LE | 40 | 0.7 Mb | 150 | 4 XCVR 3.125 Gb/s | Gen2 | — |
| 5CGXC3Altera Cyclone V | 13,460 ALMs | 36K LE | 57 | 1.3 Mb | 208 | 3 XCVR 3.125 Gb/s | Gen1 | — |
Compare side by side: XC6SLX25T vs LFE5UM-25, XC6SLX25T vs LFE5UM5G-25, XC6SLX25T vs M2GL025, XC6SLX25T vs LFMXO5-30TD, XC6SLX25T vs EP4CGX22.
Compare the XC6SLX25T with up to three other FPGAs.
XC6SLX25T quick facts
How many LUTs does the XC6SLX25T have?
The XC6SLX25T has 15,032 LUT6 look-up tables (24,051 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.
How many DSP blocks does the XC6SLX25T have?
The XC6SLX25T has 38 DSP48A1 slices and 0.9 Mb of block RAM.
Does the XC6SLX25T have transceivers?
Yes, 2 GTP transceivers at up to 3.2 Gb/s.
What are the alternatives to the XC6SLX25T?
Devices of similar size in other families include LFE5UM-25 (Lattice ECP5), LFE5UM5G-25 (Lattice ECP5), M2GL025 (Microchip IGLOO2).
Which software is used to design with the XC6SLX25T?
Designs for the XC6SLX25T are built with AMD ISE Design Suite.
Other Spartan-6 devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XC6SLX4 | 2,400 LUT6 | 3.8K LC | 8 | 0.2 Mb | 132 | — | — | — |
| XC6SLX9 | 5,720 LUT6 | 9.2K LC | 16 | 0.6 Mb | 200 | — | — | — |
| XC6SLX16 | 9,112 LUT6 | 14.6K LC | 32 | 0.6 Mb | 232 | — | — | — |
| XC6SLX25 | 15,032 LUT6 | 24.1K LC | 38 | 0.9 Mb | 266 | — | — | — |
| XC6SLX25T | 15,032 LUT6 | 24.1K LC | 38 | 0.9 Mb | 250 | 2 GTP 3.2 Gb/s | Gen1 | — |
| XC6SLX45 | 27,288 LUT6 | 43.7K LC | 58 | 2 Mb | 358 | — | — | — |
| XC6SLX45T | 27,288 LUT6 | 43.7K LC | 58 | 2 Mb | 296 | 4 GTP 3.2 Gb/s | Gen1 | — |
| XC6SLX75 | 46,648 LUT6 | 74.6K LC | 132 | 3 Mb | 408 | — | — | — |
| XC6SLX75T | 46,648 LUT6 | 74.6K LC | 132 | 3 Mb | 348 | 8 GTP 3.2 Gb/s | Gen1 | — |
| XC6SLX100 | 63,288 LUT6 | 101K LC | 180 | 4.7 Mb | 480 | — | — | — |
| XC6SLX100T | 63,288 LUT6 | 101K LC | 180 | 4.7 Mb | 498 | 8 GTP 3.2 Gb/s | Gen1 | — |
| XC6SLX150 | 92,152 LUT6 | 147K LC | 180 | 4.7 Mb | 576 | — | — | — |
| XC6SLX150T | 92,152 LUT6 | 147K LC | 180 | 4.7 Mb | 540 | 8 GTP 3.2 Gb/s | Gen1 | — |
Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.