XC6SLX45

AMDSpartan-6

The XC6SLX45 is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 27,288 LUT6 look-up tables (43,661 logic cells), 54,576 flip-flops, 2 Mb of block RAM and 58 DSP48A1 slices. It offers up to 358 user I/O pins. It is available in 4 packages, from the CSG324 (15 × 15 mm) to the FGG676 (27 × 27 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.

27,288LUTs (LUT6)

58DSP48A1 slices

2 MbBlock RAM

358Max. user I/O

—Transceivers

Specifications

Vendor	AMD
Family	Spartan-6
Series	6 Series
Process	45 nm
Configuration memory	SRAM
Look-up tables (LUT6)	27,288
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈43,661
Logic cells	43,661
Flip-flops	54,576
Distributed RAM	401 Kb
Block RAM	2 Mb (116 × 18 Kb)
DSP (DSP48A1 slice)	58
Clock management tiles	4

Max. user I/O	358
Transceivers	None
PCI Express	None
Hard memory controller	2 × MCB (DDR/DDR2/DDR3/LPDDR)
Analog / monitor	None
Design tool	AMD ISE Design Suite

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
CSG324	15 × 15	0.8	218	—
FGG484	23 × 23	1.0	316	—
CSG484	19 × 19	0.8	320	—
FGG676	27 × 27	1.0	358	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-3, -3N, -2, -1L
Industrial (I)	−40 to 100 °C	-3, -3N, -2, -1L

Alternatives to the XC6SLX45

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
LFE5U-45Lattice ECP5	44,000 LUT4	—	72	1.9 Mb	245	—	—	—
5CEA4Altera Cyclone V	18,480 ALMs	49K LE	66	3 Mb	224	—	—	—
LIFCL-40Lattice CrossLink-NX	32,500 LUT4	39K LC	56	1.5 Mb	191	—	Gen2	—
GW2A-55Gowin Arora II	54,720 LUT4	—	40	2.5 Mb	608	—	—	—
XCSU35PAMD Spartan UltraScale+	16,000 LUT6	36K SLC	48	1.7 Mb	304	—	—	—
LFD2NX-35Lattice Certus-NX	29,167 LUT4	35K LC	48	1.9 Mb	371	1 SERDES 5 Gb/s	Gen2	—

Compare side by side: XC6SLX45 vs LFE5U-45, XC6SLX45 vs 5CEA4, XC6SLX45 vs LIFCL-40, XC6SLX45 vs GW2A-55.

Compare the XC6SLX45 with up to three other FPGAs.

XC6SLX45 quick facts

How many LUTs does the XC6SLX45 have?

The XC6SLX45 has 27,288 LUT6 look-up tables (43,661 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC6SLX45 have?

The XC6SLX45 has 58 DSP48A1 slices and 2 Mb of block RAM.

Does the XC6SLX45 have transceivers?

No, the XC6SLX45 has no multi-gigabit transceivers. Its user I/O supports up to 358 pins.

What are the alternatives to the XC6SLX45?

Devices of similar size in other families include LFE5U-45 (Lattice ECP5), 5CEA4 (Altera Cyclone V), LIFCL-40 (Lattice CrossLink-NX).

Which software is used to design with the XC6SLX45?

Designs for the XC6SLX45 are built with AMD ISE Design Suite.

Other Spartan-6 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC6SLX4	2,400 LUT6	3.8K LC	8	0.2 Mb	132	—	—	—
XC6SLX9	5,720 LUT6	9.2K LC	16	0.6 Mb	200	—	—	—
XC6SLX16	9,112 LUT6	14.6K LC	32	0.6 Mb	232	—	—	—
XC6SLX25	15,032 LUT6	24.1K LC	38	0.9 Mb	266	—	—	—
XC6SLX25T	15,032 LUT6	24.1K LC	38	0.9 Mb	250	2 GTP 3.2 Gb/s	Gen1	—
XC6SLX45	27,288 LUT6	43.7K LC	58	2 Mb	358	—	—	—
XC6SLX45T	27,288 LUT6	43.7K LC	58	2 Mb	296	4 GTP 3.2 Gb/s	Gen1	—
XC6SLX75	46,648 LUT6	74.6K LC	132	3 Mb	408	—	—	—
XC6SLX75T	46,648 LUT6	74.6K LC	132	3 Mb	348	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX100	63,288 LUT6	101K LC	180	4.7 Mb	480	—	—	—
XC6SLX100T	63,288 LUT6	101K LC	180	4.7 Mb	498	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX150	92,152 LUT6	147K LC	180	4.7 Mb	576	—	—	—
XC6SLX150T	92,152 LUT6	147K LC	180	4.7 Mb	540	8 GTP 3.2 Gb/s	Gen1	—

Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.