FPGA & adaptive SoC databook · online editionRev. 2026.10

XC6SLX100

AMDSpartan-6

The XC6SLX100 is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 63,288 LUT6 look-up tables (101,261 logic cells), 126,576 flip-flops, 4.7 Mb of block RAM and 180 DSP48A1 slices. It offers up to 480 user I/O pins. It is available in 3 packages, from the CSG484 (19 × 19 mm) to the FGG676 (27 × 27 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.

63,288LUTs (LUT6)
180DSP48A1 slices
4.7 MbBlock RAM
480Max. user I/O
—Transceivers

Specifications

VendorAMD
FamilySpartan-6
Series6 Series
Process45 nm
Configuration memorySRAM
Look-up tables (LUT6)63,288
   Logic block6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)≈101,261
Logic cells101,261
Flip-flops126,576
Distributed RAM976 Kb
Block RAM4.7 Mb (268 × 18 Kb)
DSP (DSP48A1 slice)180
Clock management tiles6
Max. user I/O480
TransceiversNone
PCI ExpressNone
Hard memory controller4 × MCB (DDR/DDR2/DDR3/LPDDR)
Analog / monitorNone
Design toolAMD ISE Design Suite

Packages

PackageSize (mm)Pitch (mm)User I/OTransceivers
FGG48423 × 231.0326—
CSG48419 × 190.8338—
FGG67627 × 271.0480—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature gradeJunction rangeSpeed grades
Commercial (C)0 to 85 °C-3, -3N, -2, -1L
Industrial (I)−40 to 100 °C-3, -3N, -2, -1L

Alternatives to the XC6SLX100

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

DeviceLUTsVendor logicDSPBlock RAMMax I/OTransceiversPCIeCoreScore
XC7S100AMD Spartan-764,000 LUT6102K LC1604.2 Mb400———
5CEA7Altera Cyclone V56,480 ALMs150K LE1566.7 Mb480———
LFE5U-85Lattice ECP584,000 LUT4—1563.7 Mb365——135 ulx3s_85
EP4CE115Altera Cyclone IV114,000 LUT4114K LE2663.8 Mb528———
Ti95Efinix Titanium— 93.2K LEs, LUTs not published93.2K LE2104.5 Mb241———
T85Efinix Trion— 84.1K LEs, LUTs not published84.1K LE2404 Mb278———

Compare side by side: XC6SLX100 vs XC7S100, XC6SLX100 vs 5CEA7, XC6SLX100 vs LFE5U-85, XC6SLX100 vs EP4CE115.

Compare the XC6SLX100 with up to three other FPGAs.

XC6SLX100 quick facts

How many LUTs does the XC6SLX100 have?

The XC6SLX100 has 63,288 LUT6 look-up tables (101,261 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC6SLX100 have?

The XC6SLX100 has 180 DSP48A1 slices and 4.7 Mb of block RAM.

Does the XC6SLX100 have transceivers?

No, the XC6SLX100 has no multi-gigabit transceivers. Its user I/O supports up to 480 pins.

What are the alternatives to the XC6SLX100?

Devices of similar size in other families include XC7S100 (AMD Spartan-7), 5CEA7 (Altera Cyclone V), LFE5U-85 (Lattice ECP5).

Which software is used to design with the XC6SLX100?

Designs for the XC6SLX100 are built with AMD ISE Design Suite.

Other Spartan-6 devices

DeviceLUTsVendor logicDSPBlock RAMMax I/OTransceiversPCIeCoreScore
XC6SLX42,400 LUT63.8K LC80.2 Mb132———
XC6SLX95,720 LUT69.2K LC160.6 Mb200———
XC6SLX169,112 LUT614.6K LC320.6 Mb232———
XC6SLX2515,032 LUT624.1K LC380.9 Mb266———
XC6SLX25T15,032 LUT624.1K LC380.9 Mb2502 GTP 3.2 Gb/sGen1—
XC6SLX4527,288 LUT643.7K LC582 Mb358———
XC6SLX45T27,288 LUT643.7K LC582 Mb2964 GTP 3.2 Gb/sGen1—
XC6SLX7546,648 LUT674.6K LC1323 Mb408———
XC6SLX75T46,648 LUT674.6K LC1323 Mb3488 GTP 3.2 Gb/sGen1—
XC6SLX10063,288 LUT6101K LC1804.7 Mb480———
XC6SLX100T63,288 LUT6101K LC1804.7 Mb4988 GTP 3.2 Gb/sGen1—
XC6SLX15092,152 LUT6147K LC1804.7 Mb576———
XC6SLX150T92,152 LUT6147K LC1804.7 Mb5408 GTP 3.2 Gb/sGen1—

Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.