XC6SLX75

AMDSpartan-6

The XC6SLX75 is a Spartan-6 FPGA from AMD, built on a 45 nm process. It provides 46,648 LUT6 look-up tables (74,637 logic cells), 93,296 flip-flops, 3 Mb of block RAM and 132 DSP48A1 slices. It offers up to 408 user I/O pins. It is available in 3 packages, from the CSG484 (19 × 19 mm) to the FGG676 (27 × 27 mm). Temperature grades: commercial, industrial. Designs are built with AMD ISE Design Suite.

46,648LUTs (LUT6)

132DSP48A1 slices

3 MbBlock RAM

408Max. user I/O

—Transceivers

Specifications

Vendor	AMD
Family	Spartan-6
Series	6 Series
Process	45 nm
Configuration memory	SRAM
Look-up tables (LUT6)	46,648
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈74,637
Logic cells	74,637
Flip-flops	93,296
Distributed RAM	692 Kb
Block RAM	3 Mb (172 × 18 Kb)
DSP (DSP48A1 slice)	132
Clock management tiles	6

Max. user I/O	408
Transceivers	None
PCI Express	None
Hard memory controller	4 × MCB (DDR/DDR2/DDR3/LPDDR)
Analog / monitor	None
Design tool	AMD ISE Design Suite

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
FGG484	23 × 23	1.0	280	—
CSG484	19 × 19	0.8	328	—
FGG676	27 × 27	1.0	408	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-3, -3N, -2, -1L
Industrial (I)	−40 to 100 °C	-3, -3N, -2, -1L

Alternatives to the XC6SLX75

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC7S75AMD Spartan-7	48,000 LUT6	76.8K LC	140	3.2 Mb	400	—	—	—
LFE5U-85Lattice ECP5	84,000 LUT4	—	156	3.7 Mb	365	—	—	135 ulx3s_85
EP4CE55Altera Cyclone IV	56,000 LUT4	56K LE	154	2.3 Mb	374	—	—	—
GW5A-60Gowin Arora V	59,904 LUT4	—	118	2.1 Mb	320	—	—	—
T55Efinix Trion	— 54.2K LEs, LUTs not published	54.2K LE	150	2.7 Mb	278	—	—	—
EP4CE75Altera Cyclone IV	75,000 LUT4	75K LE	200	2.7 Mb	426	—	—	—

Compare side by side: XC6SLX75 vs XC7S75, XC6SLX75 vs LFE5U-85, XC6SLX75 vs EP4CE55.

Compare the XC6SLX75 with up to three other FPGAs.

XC6SLX75 quick facts

How many LUTs does the XC6SLX75 have?

The XC6SLX75 has 46,648 LUT6 look-up tables (74,637 logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC6SLX75 have?

The XC6SLX75 has 132 DSP48A1 slices and 3 Mb of block RAM.

Does the XC6SLX75 have transceivers?

No, the XC6SLX75 has no multi-gigabit transceivers. Its user I/O supports up to 408 pins.

What are the alternatives to the XC6SLX75?

Devices of similar size in other families include XC7S75 (AMD Spartan-7), LFE5U-85 (Lattice ECP5), EP4CE55 (Altera Cyclone IV).

Which software is used to design with the XC6SLX75?

Designs for the XC6SLX75 are built with AMD ISE Design Suite.

Other Spartan-6 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC6SLX4	2,400 LUT6	3.8K LC	8	0.2 Mb	132	—	—	—
XC6SLX9	5,720 LUT6	9.2K LC	16	0.6 Mb	200	—	—	—
XC6SLX16	9,112 LUT6	14.6K LC	32	0.6 Mb	232	—	—	—
XC6SLX25	15,032 LUT6	24.1K LC	38	0.9 Mb	266	—	—	—
XC6SLX25T	15,032 LUT6	24.1K LC	38	0.9 Mb	250	2 GTP 3.2 Gb/s	Gen1	—
XC6SLX45	27,288 LUT6	43.7K LC	58	2 Mb	358	—	—	—
XC6SLX45T	27,288 LUT6	43.7K LC	58	2 Mb	296	4 GTP 3.2 Gb/s	Gen1	—
XC6SLX75	46,648 LUT6	74.6K LC	132	3 Mb	408	—	—	—
XC6SLX75T	46,648 LUT6	74.6K LC	132	3 Mb	348	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX100	63,288 LUT6	101K LC	180	4.7 Mb	480	—	—	—
XC6SLX100T	63,288 LUT6	101K LC	180	4.7 Mb	498	8 GTP 3.2 Gb/s	Gen1	—
XC6SLX150	92,152 LUT6	147K LC	180	4.7 Mb	576	—	—	—
XC6SLX150T	92,152 LUT6	147K LC	180	4.7 Mb	540	8 GTP 3.2 Gb/s	Gen1	—

Source: Spartan-6 Family Overview, DS160 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.