5AGZE7
AlteraArria VSoCThe 5AGZE7 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 169,800 adaptive logic modules (ALMs) (450,000 logic elements (LEs)), 679,200 flip-flops, 33.2 Mb of block RAM and 1,139 variable-precision DSP blocks. It offers up to 674 user I/O pins and 36 XCVR transceivers at up to 12.5 Gb/s, with hard PCI Express Gen3 x8 blocks. It is available in 2 packages, from the F1152 (35 × 35 mm) to the F1517 (40 × 40 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Arria V |
| Series | Arria |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 169,800 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| LUT4 equivalent (approx.) | ≈339,600 |
| Logic elements (LEs) | 450,000 |
| Flip-flops | 679,200 |
| Distributed RAM | 5,306 Kb |
| Block RAM | 33.2 Mb (1700 × 20 Kb) |
| DSP (variable-precision DSP block) | 1,139 |
| Max. user I/O | 674 |
|---|---|
| XCVR transceivers | 36 × 12.5 Gb/s |
| PCI Express | Gen3 x8 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F1152 | 35 × 35 | 1.0 | 534 | 24 |
| F1517 | 40 × 40 | 1.0 | 674 | 36 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5AGZE7
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XC7VX330TAMD Virtex-7 | 204,000 LUT6 | 326K LC | 1,120 | 26.4 Mb | 700 | 28 GTH 13.1 Gb/s | Gen3 | — |
| 10AX048Altera Arria 10 | 181,790 ALMs | 629K LE | 1,368 | 28.1 Mb | 492 | 36 XCVR 17.4 Gb/s | Gen3 | — |
| 5SGSD5Altera Stratix V | 172,600 ALMs | 457K LE | 1,590 | 39.3 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | 1,152 storeypeak |
| XC6VSX315TAMD Virtex-6 | 196,800 LUT6 | 315K LC | 1,344 | 24.8 Mb | 720 | 24 GTX 6.6 Gb/s | Gen2 | — |
| 10AX057Altera Arria 10 | 217,080 ALMs | 747K LE | 1,523 | 35.2 Mb | 696 | 48 XCVR 17.4 Gb/s | Gen3 | — |
| RTPF500TMicrochip RT PolarFire | 481,000 LUT4 | 481K LE | 1,480 | 29.7 Mb | 632 | 24 SERDES 12.7 Gb/s | Gen2 | — |
Compare side by side: 5AGZE7 vs XC7VX330T, 5AGZE7 vs 10AX048, 5AGZE7 vs 5SGSD5.
Compare the 5AGZE7 with up to three other FPGAs.
5AGZE7 quick facts
How many LUTs does the 5AGZE7 have?
The 5AGZE7 has 169,800 adaptive logic modules (ALMs) (450,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5AGZE7 have?
The 5AGZE7 has 1,139 variable-precision DSP blocks and 33.2 Mb of block RAM.
Does the 5AGZE7 have transceivers?
Yes, 36 XCVR transceivers at up to 12.5 Gb/s.
What are the alternatives to the 5AGZE7?
Devices of similar size in other families include XC7VX330T (AMD Virtex-7), 10AX048 (Altera Arria 10), 5SGSD5 (Altera Stratix V).
Which software is used to design with the 5AGZE7?
Designs for the 5AGZE7 are built with Altera Quartus Prime.
Other Arria V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5AGXA1 | 28,302 ALMs | 75K LE | 240 | 7.8 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGXA3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 7 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXA5 | 71,698 ALMs | 190K LE | 600 | 11.5 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE1 | 83,020 ALMs | 220K LE | 800 | 11.4 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXA7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB1 | 113,208 ALMs | 300K LE | 920 | 14.8 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASXB3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE3 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE5 | 150,960 ALMs | 400K LE | 1,092 | 28.1 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB5 | 158,491 ALMs | 420K LE | 1,092 | 20.1 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE7 | 169,800 ALMs | 450K LE | 1,139 | 33.2 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5ASXB5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 26 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.