5ASTD5

AlteraArria VSoC

The 5ASTD5 is an Arria V SoC FPGA from Altera, built on a 28 nm process. It provides 174,340 adaptive logic modules (ALMs) (462,000 logic elements (LEs)), 697,360 flip-flops, 22.3 Mb of block RAM and 1,090 variable-precision DSP blocks. Its processing system includes two Arm Cortex-A9 cores running at up to 1.05 GHz. The programmable logic offers up to 540 user I/O pins and 46 XCVR/XCVR transceivers at up to 10.3125 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 3 packages, from the F896 (31 × 31 mm) to the F1517 (40 × 40 mm). Designs are built with Altera Quartus Prime.

174,340ALMs

1,090variable-precision DSP blocks

22.3 MbBlock RAM

540Max. user I/O

46Transceivers (10.3125 Gb/s)

2× A9Hard processor

Specifications

Vendor	Altera
Family	Arria V
Series	Arria
Process	28 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	174,340
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈348,680
Logic elements (LEs)	462,000
Flip-flops	697,360
Distributed RAM	2,658 Kb
Block RAM	22.3 Mb (2282 × 10 Kb)
DSP (variable-precision DSP block)	1,090

Max. user I/O	540
XCVR transceivers	30 × 6.5536 Gb/s
XCVR transceivers	16 × 10.3125 Gb/s
PCI Express (PL)	2× Gen2 x4
Analog / monitor	None
Hard processor	2× Arm Cortex-A9 @ 1.05 GHz
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
F896	31 × 31	1.0	250	208	18
F1152	35 × 35	1.0	385	208	26
F1517	40 × 40	1.0	540	208	46

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the 5ASTD5

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
Ti450Efinix Titanium	— 448K LEs, LUTs not published	448K LE	862	26.6 Mb	480	24 SERDES 25.8 Gb/s	Gen4	—
A5E 065AAltera Agilex 5 E-Series	222,400 ALMs	656K LE	846	31.5 Mb	504	24 XCVR 28 Gb/s	Gen4	—
A5E 065BAltera Agilex 5 E-Series	222,400 ALMs	656K LE	846	31.5 Mb	504	24 XCVR 17 Gb/s	Gen4	1,327 agilex5_dk-a5e065bb32aes1
A5E 052AAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 28 Gb/s	Gen4	—
A5E 052BAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 17 Gb/s	Gen4	—
MPFS460TMicrochip PolarFire SoC	461,000 LUT4	461K LE	1,420	28.5 Mb	468	20 SERDES 12.5 Gb/s	Gen2	—

Compare side by side: 5ASTD5 vs Ti450, 5ASTD5 vs A5E 065A, 5ASTD5 vs A5E 065B.

Compare the 5ASTD5 with up to three other FPGAs.

5ASTD5 quick facts

How many LUTs does the 5ASTD5 have?

The 5ASTD5 has 174,340 adaptive logic modules (ALMs) (462,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the 5ASTD5 have?

The 5ASTD5 has 1,090 variable-precision DSP blocks and 22.3 Mb of block RAM.

Does the 5ASTD5 have transceivers?

Yes, 46 XCVR/XCVR transceivers at up to 10.3125 Gb/s.

Does the 5ASTD5 have a processor?

Yes. It includes a hard 2× Arm Cortex-A9 processor.

What are the alternatives to the 5ASTD5?

Devices of similar size in other families include Ti450 (Efinix Titanium), A5E 065A (Altera Agilex 5 E-Series), A5E 065B (Altera Agilex 5 E-Series).

Which software is used to design with the 5ASTD5?

Designs for the 5ASTD5 are built with Altera Quartus Prime.

Other Arria V devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
5AGXA1	28,302 ALMs	75K LE	240	7.8 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
5AGXA3	58,900 ALMs	156K LE	396	10.3 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
5AGTC3	58,900 ALMs	156K LE	396	10.3 Mb	416	7 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXA5	71,698 ALMs	190K LE	600	11.5 Mb	544	24 XCVR 6.5536 Gb/s	Gen2	—
5AGZE1	83,020 ALMs	220K LE	800	11.4 Mb	414	24 XCVR 12.5 Gb/s	Gen3	—
5AGXA7	91,680 ALMs	242K LE	800	13.3 Mb	544	24 XCVR 6.5536 Gb/s	Gen2	—
5AGTC7	91,680 ALMs	242K LE	800	13.3 Mb	544	18 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXB1	113,208 ALMs	300K LE	920	14.8 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5ASXB3	132,075 ALMs	350K LE	809	16.9 Mb	540	30 XCVR 6.5536 Gb/s	Gen2	—
5ASTD3	132,075 ALMs	350K LE	809	16.9 Mb	540	46 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGZE3	135,840 ALMs	360K LE	1,044	18.7 Mb	414	24 XCVR 12.5 Gb/s	Gen3	—
5AGXB3	136,880 ALMs	362K LE	1,045	16.9 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5AGTD3	136,880 ALMs	362K LE	1,045	16.9 Mb	704	18 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGZE5	150,960 ALMs	400K LE	1,092	28.1 Mb	674	36 XCVR 12.5 Gb/s	Gen3	—
5AGXB5	158,491 ALMs	420K LE	1,092	20.1 Mb	704	36 XCVR 6.5536 Gb/s	Gen2	—
5AGZE7	169,800 ALMs	450K LE	1,139	33.2 Mb	674	36 XCVR 12.5 Gb/s	Gen3	—
5ASXB5	174,340 ALMs	462K LE	1,090	22.3 Mb	540	30 XCVR 6.5536 Gb/s	Gen2	—
5ASTD5	174,340 ALMs	462K LE	1,090	22.3 Mb	540	46 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXB7	190,240 ALMs	504K LE	1,156	23.6 Mb	704	36 XCVR 6.5536 Gb/s	Gen2	—
5AGTD7	190,240 ALMs	504K LE	1,156	23.6 Mb	704	26 XCVR/XCVR 10.3125 Gb/s	Gen2	—

Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.