5AGTC7
AlteraArria VSoCThe 5AGTC7 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 91,680 adaptive logic modules (ALMs) (242,000 logic elements (LEs)), 366,720 flip-flops, 13.3 Mb of block RAM and 800 variable-precision DSP blocks. It offers up to 544 user I/O pins and 18 XCVR/XCVR transceivers at up to 10.3125 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 2 packages, from the F896 (31 × 31 mm) to the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Arria V |
| Series | Arria |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 91,680 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| LUT4 equivalent (approx.) | ≈183,360 |
| Logic elements (LEs) | 242,000 |
| Flip-flops | 366,720 |
| Distributed RAM | 1,448 Kb |
| Block RAM | 13.3 Mb (1366 × 10 Kb) |
| DSP (variable-precision DSP block) | 800 |
| Max. user I/O | 544 |
|---|---|
| XCVR transceivers | 6 × 6.5536 Gb/s |
| XCVR transceivers | 12 × 10.3125 Gb/s |
| PCI Express | 2× Gen2 x4 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F896 | 31 × 31 | 1.0 | 384 | 14 |
| F1152 | 35 × 35 | 1.0 | 544 | 18 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5AGTC7
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XC7A200TAMD Artix-7 | 134,600 LUT6 | 215K LC | 740 | 12.8 Mb | 500 | 16 GTP 6.6 Gb/s | Gen2 | 652 nexys_video |
| XC6VLX195TAMD Virtex-6 | 124,800 LUT6 | 200K LC | 640 | 12.1 Mb | 600 | 20 GTX 6.6 Gb/s | Gen2 | — |
| 10AX027Altera Arria 10 | 101,620 ALMs | 354K LE | 830 | 14.7 Mb | 384 | 24 XCVR 17.4 Gb/s | Gen3 | — |
| EP2AGZ225Altera Arria II | 89,600 ALMs | 224K LE | 800 | 10.8 Mb | 734 | 24 XCVR 6.375 Gb/s | Gen2 | — |
| 5SGSD3Altera Stratix V | 89,000 ALMs | 236K LE | 600 | 13.4 Mb | 432 | 24 GX 14.1 Gb/s | Gen3 | — |
| XC6VLX240TAMD Virtex-6 | 150,720 LUT6 | 241K LC | 768 | 14.6 Mb | 720 | 24 GTX 6.6 Gb/s | Gen2 | — |
Compare side by side: 5AGTC7 vs XC7A200T, 5AGTC7 vs XC6VLX195T, 5AGTC7 vs 10AX027, 5AGTC7 vs EP2AGZ225.
Compare the 5AGTC7 with up to three other FPGAs.
5AGTC7 quick facts
How many LUTs does the 5AGTC7 have?
The 5AGTC7 has 91,680 adaptive logic modules (ALMs) (242,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5AGTC7 have?
The 5AGTC7 has 800 variable-precision DSP blocks and 13.3 Mb of block RAM.
Does the 5AGTC7 have transceivers?
Yes, 18 XCVR/XCVR transceivers at up to 10.3125 Gb/s.
What are the alternatives to the 5AGTC7?
Devices of similar size in other families include XC7A200T (AMD Artix-7), XC6VLX195T (AMD Virtex-6), 10AX027 (Altera Arria 10).
Which software is used to design with the 5AGTC7?
Designs for the 5AGTC7 are built with Altera Quartus Prime.
Other Arria V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5AGXA1 | 28,302 ALMs | 75K LE | 240 | 7.8 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGXA3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 7 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXA5 | 71,698 ALMs | 190K LE | 600 | 11.5 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE1 | 83,020 ALMs | 220K LE | 800 | 11.4 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXA7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB1 | 113,208 ALMs | 300K LE | 920 | 14.8 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASXB3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE3 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE5 | 150,960 ALMs | 400K LE | 1,092 | 28.1 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB5 | 158,491 ALMs | 420K LE | 1,092 | 20.1 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE7 | 169,800 ALMs | 450K LE | 1,139 | 33.2 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5ASXB5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 26 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.