5ASXB3

AlteraArria VSoC

The 5ASXB3 is an Arria V SoC FPGA from Altera, built on a 28 nm process. It provides 132,075 adaptive logic modules (ALMs) (350,000 logic elements (LEs)), 528,300 flip-flops, 16.9 Mb of block RAM and 809 variable-precision DSP blocks. Its processing system includes two Arm Cortex-A9 cores running at up to 1.05 GHz. The programmable logic offers up to 540 user I/O pins and 30 XCVR transceivers at up to 6.5536 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 3 packages, from the F896 (31 × 31 mm) to the F1517 (40 × 40 mm). Designs are built with Altera Quartus Prime.

132,075ALMs

809variable-precision DSP blocks

16.9 MbBlock RAM

540Max. user I/O

30Transceivers (6.5536 Gb/s)

2× A9Hard processor

Specifications

Vendor	Altera
Family	Arria V
Series	Arria
Process	28 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	132,075
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈264,150
Logic elements (LEs)	350,000
Flip-flops	528,300
Distributed RAM	2,014 Kb
Block RAM	16.9 Mb (1729 × 10 Kb)
DSP (variable-precision DSP block)	809

Max. user I/O	540
XCVR transceivers	30 × 6.5536 Gb/s
PCI Express (PL)	2× Gen2 x4
Analog / monitor	None
Hard processor	2× Arm Cortex-A9 @ 1.05 GHz
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
F896	31 × 31	1.0	250	208	12
F1152	35 × 35	1.0	385	208	18
F1517	40 × 40	1.0	540	208	30

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the 5ASXB3

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
MPFS250TMicrochip PolarFire SoC	254,000 LUT4	254K LE	784	15.9 Mb	372	16 SERDES 12.5 Gb/s	Gen2	—
XC7Z035AMD Zynq 7000	171,900 LUT6	275K LC	900	17.6 Mb	362	16 GTX 12.5 Gb/s	Gen2	—
Ti240Efinix Titanium	232,240 LUT4	237K LE	860	17.6 Mb	337	16 SERDES 16 Gb/s	Gen4	—
A5E 052AAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 28 Gb/s	Gen4	—
A5E 052BAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 17 Gb/s	Gen4	—
Ti260Efinix Titanium	— 264K LEs, LUTs not published	264K LE	960	19.7 Mb	310	16 SERDES 16 Gb/s	Gen4	—

Compare side by side: 5ASXB3 vs MPFS250T, 5ASXB3 vs XC7Z035, 5ASXB3 vs Ti240.

Compare the 5ASXB3 with up to three other FPGAs.

5ASXB3 quick facts

How many LUTs does the 5ASXB3 have?

The 5ASXB3 has 132,075 adaptive logic modules (ALMs) (350,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the 5ASXB3 have?

The 5ASXB3 has 809 variable-precision DSP blocks and 16.9 Mb of block RAM.

Does the 5ASXB3 have transceivers?

Yes, 30 XCVR transceivers at up to 6.5536 Gb/s.

Does the 5ASXB3 have a processor?

Yes. It includes a hard 2× Arm Cortex-A9 processor.

What are the alternatives to the 5ASXB3?

Devices of similar size in other families include MPFS250T (Microchip PolarFire SoC), XC7Z035 (AMD Zynq 7000), Ti240 (Efinix Titanium).

Which software is used to design with the 5ASXB3?

Designs for the 5ASXB3 are built with Altera Quartus Prime.

Other Arria V devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
5AGXA1	28,302 ALMs	75K LE	240	7.8 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
5AGXA3	58,900 ALMs	156K LE	396	10.3 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
5AGTC3	58,900 ALMs	156K LE	396	10.3 Mb	416	7 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXA5	71,698 ALMs	190K LE	600	11.5 Mb	544	24 XCVR 6.5536 Gb/s	Gen2	—
5AGZE1	83,020 ALMs	220K LE	800	11.4 Mb	414	24 XCVR 12.5 Gb/s	Gen3	—
5AGXA7	91,680 ALMs	242K LE	800	13.3 Mb	544	24 XCVR 6.5536 Gb/s	Gen2	—
5AGTC7	91,680 ALMs	242K LE	800	13.3 Mb	544	18 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXB1	113,208 ALMs	300K LE	920	14.8 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5ASXB3	132,075 ALMs	350K LE	809	16.9 Mb	540	30 XCVR 6.5536 Gb/s	Gen2	—
5ASTD3	132,075 ALMs	350K LE	809	16.9 Mb	540	46 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGZE3	135,840 ALMs	360K LE	1,044	18.7 Mb	414	24 XCVR 12.5 Gb/s	Gen3	—
5AGXB3	136,880 ALMs	362K LE	1,045	16.9 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5AGTD3	136,880 ALMs	362K LE	1,045	16.9 Mb	704	18 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGZE5	150,960 ALMs	400K LE	1,092	28.1 Mb	674	36 XCVR 12.5 Gb/s	Gen3	—
5AGXB5	158,491 ALMs	420K LE	1,092	20.1 Mb	704	36 XCVR 6.5536 Gb/s	Gen2	—
5AGZE7	169,800 ALMs	450K LE	1,139	33.2 Mb	674	36 XCVR 12.5 Gb/s	Gen3	—
5ASXB5	174,340 ALMs	462K LE	1,090	22.3 Mb	540	30 XCVR 6.5536 Gb/s	Gen2	—
5ASTD5	174,340 ALMs	462K LE	1,090	22.3 Mb	540	46 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXB7	190,240 ALMs	504K LE	1,156	23.6 Mb	704	36 XCVR 6.5536 Gb/s	Gen2	—
5AGTD7	190,240 ALMs	504K LE	1,156	23.6 Mb	704	26 XCVR/XCVR 10.3125 Gb/s	Gen2	—

Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.