5AGZE3
AlteraArria VSoCThe 5AGZE3 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 135,840 adaptive logic modules (ALMs) (360,000 logic elements (LEs)), 543,360 flip-flops, 18.7 Mb of block RAM and 1,044 variable-precision DSP blocks. It offers up to 414 user I/O pins and 24 XCVR transceivers at up to 12.5 Gb/s, with hard PCI Express Gen3 x8 blocks. It is available in 2 packages, from the H780 (29 × 29 mm) to the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Arria V |
| Series | Arria |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 135,840 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| LUT4 equivalent (approx.) | ≈271,680 |
| Logic elements (LEs) | 360,000 |
| Flip-flops | 543,360 |
| Distributed RAM | 4,245 Kb |
| Block RAM | 18.7 Mb (957 × 20 Kb) |
| DSP (variable-precision DSP block) | 1,044 |
| Max. user I/O | 414 |
|---|---|
| XCVR transceivers | 24 × 12.5 Gb/s |
| PCI Express | Gen3 x8 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| H780 | 29 × 29 | 1.0 | 342 | 12 |
| F1152 | 35 × 35 | 1.0 | 414 | 24 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5AGZE3
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 10AX032Altera Arria 10 | 118,730 ALMs | 419K LE | 985 | 17.4 Mb | 384 | 24 XCVR 17.4 Gb/s | Gen3 | — |
| MPF300TMicrochip PolarFire | 300,000 LUT4 | 300K LE | 924 | 18.6 Mb | 512 | 16 SERDES 12.7 Gb/s | Gen2 | 882 polarfireeval |
| LAV-AT-G50Lattice Avant-G | 255,000 LUT4 | 409K LC | 1,120 | 22.7 Mb | 298 | 16 SERDES 12.5 Gb/s | — | — |
| LAV-AT-X50Lattice Avant-X | 255,000 LUT4 | 409K LC | 1,120 | 22.7 Mb | 298 | 16 SERDES 25 Gb/s | — | — |
| EP2AGZ350Altera Arria II | 139,400 ALMs | 349K LE | 1,040 | 16 Mb | 734 | 24 XCVR 6.375 Gb/s | Gen2 | — |
| 5SGSD4Altera Stratix V | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | — |
Compare side by side: 5AGZE3 vs 10AX032, 5AGZE3 vs MPF300T, 5AGZE3 vs LAV-AT-G50.
Compare the 5AGZE3 with up to three other FPGAs.
5AGZE3 quick facts
How many LUTs does the 5AGZE3 have?
The 5AGZE3 has 135,840 adaptive logic modules (ALMs) (360,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5AGZE3 have?
The 5AGZE3 has 1,044 variable-precision DSP blocks and 18.7 Mb of block RAM.
Does the 5AGZE3 have transceivers?
Yes, 24 XCVR transceivers at up to 12.5 Gb/s.
What are the alternatives to the 5AGZE3?
Devices of similar size in other families include 10AX032 (Altera Arria 10), MPF300T (Microchip PolarFire), LAV-AT-G50 (Lattice Avant-G).
Which software is used to design with the 5AGZE3?
Designs for the 5AGZE3 are built with Altera Quartus Prime.
Other Arria V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5AGXA1 | 28,302 ALMs | 75K LE | 240 | 7.8 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGXA3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 9 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC3 | 58,900 ALMs | 156K LE | 396 | 10.3 Mb | 416 | 7 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXA5 | 71,698 ALMs | 190K LE | 600 | 11.5 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE1 | 83,020 ALMs | 220K LE | 800 | 11.4 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXA7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTC7 | 91,680 ALMs | 242K LE | 800 | 13.3 Mb | 544 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB1 | 113,208 ALMs | 300K LE | 920 | 14.8 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASXB3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD3 | 132,075 ALMs | 350K LE | 809 | 16.9 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE3 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 414 | 24 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 24 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD3 | 136,880 ALMs | 362K LE | 1,045 | 16.9 Mb | 704 | 18 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGZE5 | 150,960 ALMs | 400K LE | 1,092 | 28.1 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5AGXB5 | 158,491 ALMs | 420K LE | 1,092 | 20.1 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGZE7 | 169,800 ALMs | 450K LE | 1,139 | 33.2 Mb | 674 | 36 XCVR 12.5 Gb/s | Gen3 | — |
| 5ASXB5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 30 XCVR 6.5536 Gb/s | Gen2 | — |
| 5ASTD5 | 174,340 ALMs | 462K LE | 1,090 | 22.3 Mb | 540 | 46 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
| 5AGXB7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 36 XCVR 6.5536 Gb/s | Gen2 | — |
| 5AGTD7 | 190,240 ALMs | 504K LE | 1,156 | 23.6 Mb | 704 | 26 XCVR/XCVR 10.3125 Gb/s | Gen2 | — |
Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.